Pipelined Processor Simulator

Watching a CPU pipeline resolve its own hazards, cycle by cycle

A simulator for a 5-stage pipelined CPU with a custom 32-bit instruction set, built for Computer Architecture. It runs a real assembly program through Fetch, Decode, Execute, Memory, and Writeback, and shows — cycle by cycle, in a live GUI — how the pipeline handles the problems that make pipelining hard: instructions racing each other for data, a shared memory port, and branches that turn out to have been wrong.